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Optimizing Design for JSCC Based on DP-LDPC Coeds
2019-10-08 16:09  

报 告 人:王琳 教授

时 间:2019年10月10日(星期四)下午4点

地 点:信息工程学院二楼会议室

 

报告人简介:

Lin Wang (S’99-M’03-SM’09) received the Ph.D. degree in electronics engineering from the University of Electronic Science and Technology of China in 2001. He had earned his MS in Applied Mathematics in Kunming University of Technology in 1989 and BS in Mathematics in Chongqing Normal University in 1984. From 1984 to 1986, he was a Teaching Assistant with the Mathematics Department, Chongqing Normal University. From 1989 to 2002, he was a Teaching Assistant, a Lecturer, and then an Associate Professor in applied mathematics and communication engineering with the Chongqing University of Post and Telecommunication, China. From 1995 to 1996, he spent one year with the Mathematics Department, University of New England, Australia. In 2003, he spent three months as a Visiting Researcher with the Center for Chaos and Complexity, Department of Electronic Engineering, City University of Hong Kong. In 2013, he was a Senior Visiting Researcher with the Department of ECE, UC Davis. From 2003 to present, he was a Full Professor with the School of Informatics, Xiamen University, China. He had been a Distinguished Professor with Xiamen University since 2012 to 2017. He has authored over180 journal and conference papers (over 50 IEEE journal papers). He holds 21 patents in physical layer in digital communications. His current research interests include source coding/channel coding, joint source and channel coding /decoding, chaos modulation, and their applications to wired/wireless communication and underwater acoustic communications. He has hold several IEEE Conferences as General co-chairs and TPC co-chairs and also been editors several SCI Journals. He is senior member of IEEE since 2009 and member of executive council of Chinese Institute of Electronics since 2019.

报告内容摘要:

For 6G & B6G, esp. Internet of Things (loT) there is heavy need about low power, low cost, and low delay for the connectivity chips. So the single chip design methodologies integrating different function chips together will become popular in future. As one of these cases, joint source-channel coding (JSCC) has been confirmed to achieve significant coding gain over the separate coding in finite block-length transmission. Although JSCC based on double protograph low-density parity-check (DP-LDPC)codes has been shown to be a good solution for JSCC, it still needs to be optimized to achieve a better bit error rate (BER) performance by means of coding and decoding. In this talk, I will present our global perspective in system design and share the new design principles and methods for the purpose of low decoding threshold and low error-floor.

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